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| www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC FEATURES * * * Stereo 16-Bit Oversampling Sigma-Delta A/D Converter Stereo 16-Bit Oversampling Sigma-Delta D/A Converter Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock Selectable FIR/IIR Filter With Bypassing Option Programmable Sampling Rate up to: - Max 26 Ksps With On-Chip IIR/FIR Filter - Max 104 Ksps With IIR/FIR Bypassed On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC over 13-Khz BW Smart Time Division Multiplexed (SMARTDMTM) Serial Port - Glueless 4-Wire Interface to DSP - Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device Addresses - Programming Mode to Allow On-The-Fly Reconfiguration - Continuous Data Transfer Mode to Minimize Bit Clock Speed - Support Different Sampling Rate for Each Device - Turbo Mode to Maximize Bit Clock For Faster Data Transfer and Allow Multiple Serial Devices to Share the Same Bus - Allows up to Eight Devices to be Connected to a Single Serial Port Host port - 2-Wire Interface - Selectable I2C or S2C * * Differential and Single-Ended Analog Input/Output Built-In Analog Functions: - Analog and Digital Sidetone - Antialiasing Filter (AAF) - Programmable Input and Output Gain Control (PGA) - Microphone/Handset/Headset Amplifiers - AIC20/21/20K Have a Built-In 8- Speaker Driver - Power Management With Hardware/Software Power-Down Modes 30 W Separate Software Control for ADC and DAC Power Down Fully Compatible With Common TMS320TM DSP Family and Microcontroller Power Supplies - 1.65-V - 1.95-V Digital Core Power - 1.1-V - 3.6-V Digital I/O - 2.7-V - 3.6-V Analog Internal Reference Voltage (Vref) 2s Complement Data Format Test Mode Which Includes Digital Loopback and Analog Loopback * * * * * * * * * APPLICATIONS * * * * * Wireless Accessories Hands-Free Car Kits VOIP Cable Modem Speech Processing * TLV320AIC20K and TLV320AIC24K are in the product preview stage of development. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SMARTDM, TMS320, TMS320C5000, TMS320C6000 are registered trademarks of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2005, Texas Instruments Incorporated TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-performance, dual-voice codec. It features two 16-bit analog-to-digital (A/D) channels and two 16-bit digital-to-analog (D/A) channels, which can be connected to a handset, headset, speaker, microphone, or a subscriber line via a programmable analog crosspoint. The TLV320AIC2x provides high resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology with programmable sampling rate. The TLV320AIC2x implements the smart time division multiplexed serial port (SMARTDMTM) . The SMARTDM port is a synchronous 4-wire serial port in TDM format for glue-free interface to TI DSPs (i.e., TMS320C5000TM, TMS320C6000TM DSP platforms) and microcontrollers. The SMARTDMTM supports both continuous data transfer mode and on-the-fly reconfiguration programming mode. The TLV320AIC2x can be gluelessly cascaded to any SMARTDM-based device to form a multichannel codec, and up to eight TLV320AIC2x codecs can be cascaded to a single serial port. The TLV320AIC2x provides a flexible host port. The host port interface is a two-wire serial interface that can be programmed to be either an industrial standard I2C or a simple S2C (start-stop communication protocol). The TLV320AIC2x integrates all of the critical functions needed for most voice-band applications including MIC preamplifier, handset amplifier headset amplifier, 8- speaker driver, sidetone control, antialiasing filter (AAF), input/output programmable gain amplifier (PGA), and selectable low-pass IIR/FIR filters. The TLV320AIC2x implements an extensive power management; including device power-down, independent software control for turning off ADC, DAC, operational-amplifiers, and IIR/FIR filter (bypassable) to maximize system power conservation. The TLV320AIC2x consumes only 14.9 mW per channel at 3 V. The TLV320AIC2x low power operation from 2.7-V to 3.6-V power supplies along with extensive power management make it ideal for portable applications including wireless accessories, hands-free car kits, VOIP, cable modem, and speech processing. Its low group delay characteristic makes it suitable for single or multichannel active control applications. The TLV320AIC2x is characterized for commercial operation from 0C to 70C, and industrial operation from -40C to 85C. The TLV320AIC2xk is characterized for industrial operation from -40C to 85C. ORDERING INFORMATION TA 0C to 70C -40C to 85C (1) (2) 48-TQFP PFB PACKAGE (1) (2) TLV320AIC2xC TLV320AIC2xI For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. TLV320AIC20K and TLV320AIC24K are in the product preview stage of development. 2 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 PFB TOP VIEW MICBIAS DRVSS2 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 LCDAC HNSOHNSO+ HNSIHNSI+ AVDD AVSS LINEI+ LINEILINEOLINEO+ NC DRVSS1 DRVDD SPKO+ AVDD1 AVSS1 SPKO- MICI+ CIDI+ MICI- CIDI- 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 VSS RESET MCLK M/S SCLK FS DIN DOUT DVSS DVDD FSD IOVSS TESTP PWRDN HDSO+ AVDD2 HDSO- Terminal Functions TERMINAL NAME HDSIHDSI+ HDSOHDSO+ AVDD2 AVSS2 TESTP NC PWRDN SDA SCL IOVDD IOVSS FSD DVDD DVSS DOUT DIN FS SCLK NO. 1 2 3 4 5 6 7 8, 48 9 10 11 12 13 14 15 16 17 18 19 20 I I/O I I I O I I O I I/O I/O I/O I O I I I DESCRIPTION Head-set input. The Head-set input can be treated similar to the Line-input pins 150- output Analog power supply Analog ground Test pin. Should be connected to digital ground. Not connected Power down I2C/S2C data I2C/S2C clock I/O power supply I/O ground Frame sync delayed Digital supply (1.8 V) Digital ground Data OUT Data IN Frame sync Serial clock 3 IOVDD HDSI+ NC AVSS2 HDSI- SDA SCL TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Terminal Functions (continued) TERMINAL NAME M/S MCLK RESET VSS DRVSS1 SPKO+ SPKODRVDD DRVSS2 CIDICIDI+ AVDD1 AVSS1 MICIMICI+ MICBIAS LCDAC HNSOHNSO+ HNSIHNSI+ AVDD AVSS LINEI+ LINEILINEOLINEO+ NO. 21 22 23 24 25 26 28 27 29 30 31 33 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 I/O I I I I I O I I I I I I I I O O I I I I O Master clock Reset Device ground. Typically this should be connected to the Analog Ground. Driver ground 8- output Driver supply Driver ground Caller-ID input. The Caller-ID input can be treated similar to the Line-input pins Analog supply Analog ground Microphone input Microphone input Microphone bias 6-Bit DAC output may be used to drive LCDAC 150- output Hand-set input. The Hand-set input can be treated similar to the Line-input pins Analog supply Analog ground Line input 600- output DESCRIPTION Master slave select applied to CODEC1 only. CODEC2 is always a slave. 4 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Electrical Characteristics All specifications are common across the AIC20, AIC21, AIC24, AIC25, AIC20K, and AIC24K except where explicitly stated. AIC20/21/24/25: Over Recommended Operating Free-Air Temperature Range, AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V (Unless Otherwise Noted) AIC20K/24K: Over Recommended Operating Free-Air Temperature Range, AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V (Unless Otherwise Noted) Absolute Maximum Ratings (1) over Operating Free-Air Temperature Range (Unless Otherwise Noted) TLV320AIC2x VCC VO VI TA Tstg Supply voltage range: DVDD (2) AVDD, IOVDD, DRVDD (2) Output voltage range, all digital output signals Input voltage range, all digital input signals Operating free-air temperature range Storage temperature range Case temperature for 10 seconds: package (1) (2) -0.3 V to 2.25 V -0.3 V to 4 V -0.3 V to IOVDD + 0.3 V -0.3 V to IOVDD + 0.3 V -40C to 85C -65C to 150C 260C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. Recommended Operating Conditions MIN Analog, AVDD VCC Supply voltage Analog output driver, DRVDD (1) Digital core, DVDD Digital I/O, IOVDD Analog single-ended peak-to-peak input voltage, VI(analog) Between LINEO+ and LINEO- (differential) RL Output load resistance, Between HDSO+ and HDSO- (differential) Between HNSO+ and HDSO- (differential) Between SPKO+ and SPKO- (differential) CL Analog output load capacitance Digital output capacitance Master clock ADC or DAC conversion rate TA (1) Operating free-air temperature, DRVDD should be kept at the same voltage as AVDD. -40 600 150 150 8 20 20 100 26 85 pF pF MHz kHz C 2.7 2.7 1.65 1.1 NOM 3.3 3.3 1.8 3.3 MAX 3.6 3.6 1.95 3.6 2 UNIT V V V V V 5 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Digital Inputs and Outputs FS = 8 KHz, outputs not loaded PARAMETER VOH VOL IIH IIL Ci Co High-level output voltage, DOUT Low-level output voltage, DOUT High-level input current, any digital input Low-level input current, any digital input Input capacitance Output capacitance 5 5 3 5 MIN 0.8 IOVDD 0.1 IOVDD TYP MAX UNIT V V A A pF pF ADC PATH FILTER FS = 8 KHz (1) (2) PARAMETER PATH FILTER TEST CONDITIONS 0 Hz to 60 Hz 60 Hz to 200 Hz 200 Hz to 300 Hz 300 Hz to 2.4 KHz MIN TYP FIR FILTER MAX MIN TYP IIR FILTER MAX UNIT -27 / 0.07 -1 / 0.07 -0.03 / 0.05 -0.1 -0.05 -0.5 0.15 0.15 0.1 -0.4 -26 -52 -0.1 -0.5 -0.5 -27 / 0.15 -0.75 / 0.15 0. 11 / 0.15 0.25 0.2 0.2 0.15 -42 -52 dB Filter gain relative to gain at 1020 Hz 2.4 kHz to 3 kHz 3 kHz to 3.4 KHz 3.4 kHz to 3.6 KHz 4 KHz 4.5 KHz to 72 kHz (1) (2) The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with 0 dB = 4 VI(PP) as the reference level for the analog input signal. The pass band is 0 to 3600 Hz for an 8-KHz sample rate. This pass band scales linearly with the sample rate. The filter characteristics are specified by design and are not tested in production. In places where more than one value is specified, the first value is with the High Pass Filter on and the second value is with the HPF off ADC DYNAMIC PERFORMANCE With FIR Filter, FS = 8 KHz PARAMETER Line In Driver SNR THD THD+N (1) Signal-to-noise ratio Total harmonic distortion Signal-to-harmonic distortion + noise VI = -3 dB VI = -9 dB VI = -3 dB VI = -9 dB VI = -3 dB VI = -9 dB 81 73 83 81 80 73 (1) TEST CONDITIONS MIN TYP AIC20/21/24/25 84 76 90 88 83 76 MAX MIN TYP AIC20k/24k MAX UNIT 70 70 84 76 90 88 83 76 dB The test condition is a differential 1020-Hz input signal with an 8-KHz conversion rate. Input and output common mode is 1.35 V. 6 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 ADC DYNAMIC PERFORMANCE With IIR Filter, FS = 8 KHz PARAMETER TEST CONDITIONS VI = -3 dB VI = -9 dB VI = -3 dB VI = -9 dB VI = -3 dB VI = -9 dB MIN TYP AIC20/21/24/25 SNR THD THD+N Signal-to-noise ratio Total harmonic distortion Signal-to-harmonic distortion + noise 82 76 83 77 78 70 MAX MIN TYP AIC20k/24k 82 76 83 77 78 70 dB MAX UNIT ADC CHANNEL CHARACTERISTICS PARAMETER VI(pp) VIO IB Differential-ended input level Input offset voltage Input bias current Common mode voltage Dynamic range Mute attenuation Intrachannel isolation EG EO(ADC) CMRR Gain error ADC converter offset error Common-mode rejection ratio at INMx and INPx Idle channel noise Ri Ci Input resistance Input capacitance Channel delay VI = -100 mV at 1020 Hz V(INP,INM,MICIN) = 0 V TA = 25C TA = 25C IIR FIR VI = -3 dB at 1020 Hz VI = -3 dB PGA = MUTE TEST CONDITIONS PGA gain = 0 dB 5 125 1.35 87 Zero Digital Code 87 -0.45 15 50 70 10 2 5/fs 17/fs AIC20/21/24/25/20k/24k MIN TYP MAX 4 UNIT V mV A V dB dB dB dB mV dB Vrms k pF S S DAC PATH FILTER FS = 8 KHz (1) (2) PARAMETER PATH FILTER, FS = 8 KHz TEST CONDITIONS FIR FILTER MIN TYP MAX 0.1 -0.05 -0.25 -0.3 -0.55 0.15 0.1 0.05 -30 -28 -70 -0.1 -0.2 -0.25 MIN IIR FILTER TYP MAX 0.05 0.05 0.1 0.1 0.05 0 -34 -70 dB UNIT 0 Hz to 200 Hz 200 Hz to 300 Hz 300 Hz to 2.4 KHz Filter gain relative to gain at 1020 Hz 2.4 kHz to 3 kHz 3 kHz to 3.4 KHz 3.4 kHz to 3.6 KHz 4 KHz 4.5 KHz to 72 KHZ (1) (2) The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of a sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 4 VI(PP) . The pass band is 0 to 3600 Hz for an 8-kHz sample rate. This pass band scales linearly with the conversion rate. The filter characteristics are specified by design and are not tested in production. 7 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com DAC DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS AIC20/21/24/25 MIN TYP MAX AIC20k/24k MIN TYP MAX UNIT The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. DAC Line Output (LINEO-, LINEO+) The test is measured at output of the application schematic low-pass filter. The test is conducted in Using FIR Filter 16-bit mode. SNR THD THD+N Signal-to-noise ratio Total Harmonic Distortion Signal-to-total Harmonic Distortion + noise VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB 88 81 84 77 82 76 92 83 90 84 88 80 70 80 92 83 90 84 88 80 dB The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. DAC Line Output (LINEO-, LINEO+) The test is measured at output of the application schematic low-pass filter. The test is conducted in Using IIR Filter 16-bit mode. SNR THD THD+N Signal-to-noise ratio Total Harmonic Distortion Signal-to-total Harmonic Distortion + noise VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB 83 74 85 80 80 73 83 74 85 80 80 73 dB DAC Headphone Output (HDSO-, HDSO+), (HNSO-, HNSO+) (1) SNR THD THD+N Signal-to-noise ratio Total Harmonic Distortion Signal-to-total Harmonic Distortion + noise The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of the application schematic low-pass filter. The test is conducted in 16-bit mode. VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB 92 83 90 89 88 82 92 83 90 89 88 82 dB DAC Speaker Output (SPKO-, SPKO+) (1) (2) SNR THD THD+N (1) (2) Signal-to-noise ratio Total Harmonic Distortion Signal-to-total Harmonic Distortion + noise The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of the application schematic low-pass filter. The test is conducted in 16-bit mode. VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB VI = 0 dB VI = -9 dB 91 83 91 91 88 82 91 83 91 91 88 82 dB The conversion rate is 8 kHz. The speaker driver is valid only for the AIC20/21/20K. 8 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 DAC CHANNEL CHARACTERISTICS PARAMETER Dynamic range Interchannel isolation EG Gain error, 0 dB Mute attenuation Common-mode voltage Idle channel narrow band noise VOO VO Output offset voltage at OUTP1_150 (differential) Analog output voltage, (3.3 V) Channel delay (1) The conversion rate is 8 kHz. 0 - 4 kHz (1) TEST CONDITIONS VI = 0 dB at 1020 Hz VO = 0 dB at 1020 Hz PGA = Mute MIN TYP 92 90 -0.7 90 1.35 40 8 MAX UNIT dB dB dB dB V V rms V DIN = All zeros HDSO+ IIR FIR 0.35 2.35 5/fs 18/fs V s s OUTPUT AMPLIFIER CHARACTERISTICS PARAMETER SPEAKER INTERFACE (1) TEST CONDITIONS AIC20/21/24/25/20k/24k MIN TYP 250 250 13 13 3.5 3.5 MAX UNIT mW mA mW mA mW mA Speaker output power Maximum output current HANDSET AND HEADSET INTERFACE Speaker output power Maximum output current LINE INTERFACE Speaker output power Maximum output current (1) The speaker driver is valid only for the AIC20/21/20k. VCC = 3.3 V, fully differential, 8- load VCC = 3.3 V, fully differential, 150- load VCC = 3.3 V, fully differential, 600- load BIAS AMPLIFIER CHARACTERISTICS PARAMETER VO VS Output voltage Integrated noise Offset voltage Current drive Unity gain bandwith DC gain PSRR 300 Hz - 13 KHz TEST CONDITIONS AIC20/21/24/25/20k/24k MIN TYP 1.35/2.35 20 10 5 1 90 70 MAX UNIT V V mV mA MHz dB dB POWER-SUPPLY REJECTION (1) PARAMETER AVDD (1) Supply-voltage rejection ratio, analog supply (fj = 0 to fs/2 ) TEST CONDITIONS Differential MIN TYP 75 MAX UNIT Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200 mV peak-to-peak signal applied to the appropriate supply. 9 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com POWER-CONSUMPTION PARAMETER ADC (single channel) DAC (single channel) Speaker driver Handset driver Headset driver Lineout driver Reference Digital PLL Total Analog with all sections on POWER DOWN CURRENT Hardware power-down (no clock) Software power-down (1) Analog, PLL off Digital 1 2 650 A PLL off Analog Digital No signal, PLL off (1) TEST CONDITIONS AIC20/21/24/25/20k/24k MIN TYP 5.7 3.5 9.3 2 2 2 2.3 3.4 4.6 1.8 35.8 mW MAX UNIT Without drivers No signal No signal No signal No signal The speaker driver is valid only for the AIC20/21/20k. LCD DAC PARAMETER VO Output range Sampling rate INL DNL VS EG Offset voltage Gain error 0.5 0.25 25 0.02 AIC20/21/20k MIN 0.35 TYP MAX 2.35 104 UNIT V kHz LSB LSB mV dB Typical ADC performance With PGA Gain Setting Using FIR (1) PGA GAIN SETTING 9 dB 18 dB 24 dB 36 dB (1) SNR 83 83 78 72 THD 90 97 95 95 SINAD 81 83 77 72 dB UNIT Test condition is a 1020-Hz input differential signal with an 8-kHz conversion rate. Input amplitude is given such that output of PGA is at -3 dB level. 10 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Functional Block Diagram - AIC20/21/20K Speaker 8 Output SPKO+ SPKO- Line Output 600 LINE0+ LINEOCODEC 1 (Channel 1) - DAC Analog Sidetone -9 dB to -27 dB 0dB to -42 dB (1.5 dB Steps). -48 dB, -54 dB Handset 150 Output HNSO+ HNSO- + Handset Input HNSI+ HNSI- ADC Headset 150 Output HDSO+ HDSOHDSI+ HDSI- + 0dB to 42dB (1.5 dB Steps). 48 dB, 54 dB CODEC 2 (Channel 2) - DAC 0dB to -42 dB (1.5 dB Steps). -48 dB, -54 dB 0dB to 42dB (1.5 dB Steps). 48 dB, 54 dB - ADC Headset Input Microphone Input MICI+ MICI- Line Input LINEI+ LINEIAnalog Sidetone -9 dB to -27 dB CIDI+ CIDI1.35 V / 2.35 2 mA MICBIAS LCDAC DAC SMARTDM TM Serial Port Internal Clock Generator Host Port MCLK FSD DOUT DIN SCLK FS M/S SDA SCL 11 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Functional Block Diagram - AIC24/25/24K OUTP1 OUTM1 CODEC 1 (Channel 1) - DAC Analog Sidetone -9 dB to -27 dB 0 dB to -42 dB (1.5 dB Steps). -48 dB, -54 dB Line Output 600 150 Output OUTP2 OUTM2 + Input INP2 INM2 - ADC 150 Output OUTP3 OUTM3 + 0 dB to 42 dB (1.5 dB Steps). 48 dB, 54 dB CODEC 2 (Channel 2) - DAC 0 dB to -42 dB (1.5 dB Steps). -48 dB, -54 dB 0 dB to 42 dB (1.5 dB Steps). 48 dB, 54 dB - ADC Input INP3 INM3 Microphone Input MICI+ MICI- Input INP1 INM1 Analog Sidetone -9 dB to -27 dB Input INP4 INM4 1.35 V / 2.35 2 mA MICBIAS LCDAC DAC SMARTDMTM Serial Port Internal Clock Generator Host Port MCLK FSD DOUT DIN SCLK FS M/S SDA SCL 12 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Functional Block Diagram (One of Two Channels Shown) CODEC Decimation Filter AntiAliasing Filter PGA SigmaDelta ADC Sinc Filter FIR Filter IIR Filter DOUT Digital Loopback w/ Sidetone Control and Mute -9 dB to -27 dB Interpolation Filter PGA Low Pass Filter SigmaDelta DAC Sinc Filter FIR Filter IIR Filter DIN FS SCLK FSD SMARTDM Serial Port M/S 0 dB to 42 dB (1.5 dB Steps) 48 dB, 54 dB Analog Loopback Vref 0 dB to -42 dB (1.5 dB Steps) -48 dB, -54 dB Definitions and Terminology Data Transfer Interval Signal Data The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks, and the data transfer is initiated by the falling edge of the FS signal. This refers to the input signal and all of the converted representations through the ADC channel and the signal through the DAC channel to the analog output. This is contrasted with the purely digital software control data. Frame sync refers only to the falling edge of the signal FS that initiates the data transfer interval Frame sync and sampling period is the time between falling edges of successive FS signals. The sampling frequency ADC channel refers to all signal processing circuits between the analog input and the digital conversion result at DOUT. DAC channel refers to all signal processing circuits between the digital data word applied to DIN and the differential output analog signal available at OUTP and OUTM. Bit position in the primary data word (xx is the bit number) Bit position in the secondary data word (xx is the bit number) The alpha character d represents valid programmed or default data in the control register format (see Section 3.2, Secondary Serial Communication) when discussing other data bit portions of the register. Programmable gain amplifier Infinite impulse response Finite impulse response Frame Sync Frame Sync and Sampling Period fs ADC Channel DAC channel Dxx DSxx d PGA IIR FIR 13 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com TIMING REQUIREMENTS twH MCLK twL th1 RESET 2.4 V 2.4 V 2.4 V tsu1 Figure 1. Hardware Reset Timing SCLK td1 td2 FS td1 td2 FSD ten DOUT td3 D15 tsu2 D15 tdis th2 DIN Figure 2. Serial Communication Timing TEST CONDITIONS twH twL tsu1 th1 td1 td2 td3 ten tdis tsu2 th2 Pulse duration, MCLK high Pulse duration, MCLK low Setup time, RESET, before MCLK high (see Figure 1) Hold time, RESET, after MCLK high (see Figure 1) Delay time, SCLK to FS/FSD Delay time, SCLK to FS/FSD Delay time, SCLK to DOUT Enable time, SCLK to DOUT Disable time, SCLK to DOUT Setup time, DIN, before SCLK Hold time, DIN, after SCLK 10 10 CL = 20 pF MIN 5 5 3 2 5 5 15 15 15 ns TYP MAX UNIT 14 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 SDA tf tLOW tr tSU;DAT tf tHD;STA tr tBUF SCL tHD;STA tHD;DAT tHIGH tSU;STA tSU;STO Figure 3. I2C / S2C Timing Diagram PARAMETER SCL clock frequency Hold time (repeated START condition. After this period, the first clock pulse is generated. Low period of the SCL clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition SYMBOL tSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF 100 500 MIN 0 100 560 560 100 50 50 300 100 ns MAX 900 UNIT kHz 15 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com PARAMETER MEASUREMENT INFORMATION 0 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 0 500 1000 1500 2000 2500 3000 3500 4000 f - Frequency - Hz Figure 4. FFT--ADC Channel (-3 dB input) 0 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 0 500 1000 1500 2000 2500 3000 3500 4000 f - Frequency - Hz Figure 5. FFT--ADC Channel (-9 dB input) 0 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 f - Frequency - Hz Figure 6. FFT--DAC Channel (0 dB input) 16 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION (continued) 0 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 f - Frequency - Hz Figure 7. FFT--DAC Channel (-9 dB input) 0 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 0 2000 4000 6000 8000 10000 f - Frequency - Hz 12000 14000 16000 Figure 8. FFT--ADC Channel in FIR/IIR Bypass Mode (-3 dB input) 0 -20 Amplitude - dB -40 -60 -80 -100 -120 -140 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 f - Frequency - Hz Figure 9. FFT--DAC Channel in FIR/IIR Bypass Mode (0 dB input) 17 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 5 0 Filter Gain - dB -5 -10 -15 -20 -25 -30 0 500 1000 1500 2000 2500 f - Frequency - Hz 3000 3500 4000 Figure 10. ADC FIR Frequency Response - HPF Off 10 0 Filter Gain - dB -10 -20 -30 -40 -50 -60 -70 -80 0 500 1000 1500 2000 2500 f - Frequency - Hz 3000 3500 4000 Figure 11. ADC FIR Frequency Response - HPF On 5 0 -5 Filter Gain - dB -10 -15 -20 -25 -30 -35 -40 -45 0 500 1000 1500 2000 2500 3000 3500 4000 f - Frequency - Hz Figure 12. ADC IIR Frequency Response - HPF Off 18 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION (continued) 10 0 Filter Gain - dB -10 -20 -30 -40 -50 -60 -70 -80 0 500 1000 1500 2000 2500 3000 3500 4000 f - Frequency - Hz Figure 13. ADC IIR Frequency Response - HPF On 2 0 Filter Gain - dB -2 -4 -6 -8 -10 -12 -14 0 2000 4000 6000 8000 10000 12000 14000 16000 f - Frequency - Hz Figure 14. ADC Frequency Response - FIR/IIR Bypass Mode 20 0 Filter Gain - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1000 2000 3000 4000 5000 f - Frequency - Hz 6000 7000 8000 Figure 15. DAC FIR Frequency Response 19 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 20 0 Filter Gain - dB -20 -40 -60 -80 -100 -120 -140 -160 0 1000 2000 3000 4000 5000 6000 7000 8000 f - Frequency - Hz Figure 16. DAC IIR Frequency Response 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 Filter Gain - dB 0 4000 8000 12000 16000 20000 f - Frequency - Hz 24000 28000 32000 Figure 17. DAC Channel Frequency Response - FIR/IIR Bypass Mode 20 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Functional Description Operating Frequencies The sampling frequency is the frequency of the frame sync (FS) signal where falling edge starts digital-data transfer for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the following equations: * Coarse sampling frequency (default): - The coarse sampling is selected by programming P = 8 in the control register 4, which is the default configuration of AIC2x on power-up or reset. - FS = Sampling (conversion) frequency = MCLK / (16 x M x N x 8) * Fine sampling frequency (see Note 5): - FS = Sampling (conversion) frequency = MCLK/ (16 x M x N x P) NOTE: 1. 2. 3. 4. 5. Use control register 4 to set the following values of M, N, and P M = 1, 2, . . . , 128 N = 1, 2, . . . , 16 P = 1, 2, . . . , 8 The fine sampling rate needs an on-chip phase lock loop (frequency multiplier) to generate internal clocks. The output of the PLL is only used to generate internal clocks that are needed by the data converters. Other clocks such as the serial interface clocks in master mode are not generated from the PLL output. The clock generation scheme is as shown in Figure 18. The PLL requires the relationship between MCLK and P to meet the following condition: 10 MHz (MCLK/P) 25 MHz. X8 (DLL) Digital MCLK 1/P 1/(MN) 128FS en_dll SCLK (devnum x mode)/(MNP) 1/(16 x mode x devnum) FS SCLK may not be a uniform clock depending upon value of devnum, mode, and MNP. . M = 1 - 128 N = 1 - 16 P=1-8 When: P1 = 8, DLL(PLL) is Enabled devnum = Number of Channels in Cascade. Note That for a Standalone Device, devnum = 2. Mode = 1 (For Continious Data Transfer Mode) Mode = 2 (For Programming Mode) Figure 18. Clock Timing 6. Selecting the Fine sampling mode turns on the analog PLL, which starts generating after a finite time delay. The internal clocks are required to be present in order to enable the DAC output drivers. Therefore, turning on any output drivers immediately after turning on the PLL causes the output of the DAC to go to the common-mode voltage. While using the PLL, the output drivers must first be enabled before the PLL is enabled in order to ensure correct operation of the part. This implies that register 6B for channel 1 and channel 2 in the codec must be programmed before register 4. 21 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Functional Description (continued) 7. Both equations of FS require that the following conditions should be met - (M x N x P) (devnum mode) if the FIR/IIR filter is not bypassed. - [Integer(M/4) x N x P] (devnum mode) if the FIR/IIR filter is bypassed. Where: devnum is the number of codec channels connecting in cascade (devnum = 2 for standalone AIC20) mode is equal to 1 for continuous data transfer mode and 2 for programming mode. 8. If the DAC OSR is set to 512, then M needs to be a multiple of 4. If the DAC OSR is set to 256, then M needs to be a multiple of 2. M can take any value between 1 and 128 if the OSR is set to 128. Example: The MCLK comes from the DSP C5402 CLKOUT and equals to 20.48 MHz and the conversion rate of 8 kHz is desired. First, set P = 1 to satisfy condition 5 so that (MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick M = 10 and N = 16 to satisfy condition 65 and derive 8 kHz for FS. That is, FS = 20.48 MHz/ (16 x 10 x 16 x 1) = 8 kHz. Internal Architecture Analog Low Pass Filter The built-in analog low pass antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz. Sigma-Delta ADC The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128x oversampling. The ADC provides high-resolution, low-noise performance using oversampling techniques. Decimation Filter The decimation filters consist of a sinc filter stage followed by either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter provides linear-phase output with 17/fs group delay, whereas the IIR filter generates nonlinear phase output with negligible group delay. The decimation filters reduce the digital data rate to the sampling rate. This is accomplished by decimating with a ratio of 1:128. The output of the decimation filter is a 16-bit 2s-complement data word clocking at the sample rate selected for that particular data channel. The BW of the filter is (0.45 x FS) and scales linearly with the sample rate. Sigma-Delta DAC The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128x oversampling. The DAC provides high-resolution, low-noise performance using oversampling techniques. The oversampling ratio (OSR) in DAC is programmable to 256/512 using bits D0-D1 of register 3C, the default being 128. The OSR of 512 is recommended when the FS is a maximum of 8 Ksps, and an OSR of 256 is recommended when the FS is a maximum of 16 Ksps. It is also required that the value of M used in programming the PLL be a multiple of 4 if the OSR is set to 512 and 2 if the OSR is set to 256 Interpolation Filter The interpolation filters consist of either FIR or IIR filters selected by bit D5 of control register 1 followed by a sinc filter stage. The FIR filter provides linear-phase output with 18/fs group delay, whereas the IIR filter generates nonlinear phase output with negligible group delay. The interpolation filter resamples the digital data at a rate of 128 times the incoming sample rate. The high-speed data output from the interpolation filter is then used in the sigma-delta DAC. The BW of the filter is (0.45 x FS) and scales linearly with the sample rate. 22 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Functional Description (continued) Analog/Digital Loopback The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used for in-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter output into the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the ADC output to the DAC input on the device. Analog loopback is enabled by writing a 1 to bit D2 in the control register 1. Digital loopback is enabled by writing a 1 to bit D1 in control register 1. Analog Sidetone The analog sidetone attenuates the analog input and mixes it with the output of the DAC. The control register 5C selects the attenuation level of the analog sidetone. Digital Sidetone The digital sidetone attenuates the ADC output and mixes it with the input of the DAC. The control register 5C selects the attenuation level of the digital sidetone. Analog Input/Output To produce excellent common-mode rejection of unwanted signal performance, the analog signal is processed differentially until it is converted to digital data. The signal source driving the analog inputs should have low source impedance for lowest noise performance and accuracy. To obtain maximum dynamic range, the signal must be ac coupled to the input terminal. The analog output is differential from the digital-to-analog converter. Analog Crosspoint The analog crosspoint is a lossless analog switch matrix controlled via the serial control port. It allows any source device to be connected to any sink device. Additionally, special summing connections with adjustable loss (7 x 3 dB steps) are included to implement sidetone for the headset and handset ports. (Also included is muting function on any of the sink devices). The control of the analog crosspoint, defined in the control register 6, is to allow any analog input or output to connect to a codec at one time. If more than one input is selected, these inputs are mixed together before the conversion. Caution needs to be taken to make sure that both DAC channels are not connected to the same output. Analog Input Amplifier The integrated programmable gain amplifier (PGA) controls the amplification of any analog input before the analog-to-digital converter converts the signal. The PGA's gain from 0 dB to 42 dB in 1.5-dB steps and 48 dB and 54 dB are selected using the control register 5A. Microphone Bias To operate electret microphones properly, a bias voltage and current are provided. Typically, the current drawn by the microphone is in the order of 100 A to 800 A and the bias voltage is specified across the microphone at 1.35 V or 2.35 V. The MICBIAS has good power supply noise rejection in the audio band and the bias voltage is selectable, via bit D3 of control register 1, for each interface. Output Drivers The HSNO and HDSO are output from two audio amplifiers to drive low-voltage speakers like those in the handset and headset. They can drive a load of 150 . The drive amplifier is differential to minimize noise and EMC immunity problems. The frequency response is flat up to 26 kHz. Speaker Driver The SPKO is output from the audio amplifier that can drive an 8- speaker load. The drive amplifier is differential to minimize noise and EMC immunity problems. The frequency response is flat up to 26 kHz. 23 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Functional Description (continued) IIR/FIR Control Overflow Flags The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog signal has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an overflow flag (bit D4) of control register 1 indicating that the digital input has exceeded the range of internal interpolation filter calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user reads the register. Reading this value resets the overflow flag. These flags need to be reset after power up by reading the register. If FIR/IIR overflow occurs, the input signal should be attenuated by either the PGA or some other method. IIR/FIR Bypass Mode An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This mode is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to four times normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8 kHz) with IIR/FIR, if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4x8 kHz = 32 kHz. The sync filters of the two paths can not be bypassed. A maximum of four devices in cascade can be supported in the IIR/FIR bypass mode. In this mode , the ADC channel outputs data which has been decimated only till 4 FS. Similarly DAC channel input needs to be preinterpolated to 4 FS before being given to the device. This mode allows users the flexibility to implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR bypass mode. System Reset and Power Management Software and Hardware Reset The TLV320AIC2x resets internal counters and registers in response to either of two events: * A low-going reset pulse is applied to terminal RESET * A 1 is written to the programmable software reset bits (D3 of control register 3A) NOTE: The TLV320AIC2x requires a power-up reset applied to the RESET pin. Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active low) signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC2x enters the initialization cycle that lasts for 132 MCLKs, during which the serial port of the DSP must be 3-stated. The initialization sequence performed by the AIC2x is known as Auto Cascade Detection (ACD). ACD is a mechanism that allows a device to know its address in a cascade chain. Up to 8 AIC2x devices can be cascaded together. The Master device is the first device on the chain i.e. the FS of the Master is connected to the FS of the DSP. During ACD, each device gets to know the number of devices in the chain as well as its relative position in the chain. This is done upon hardware reset. Therefore. after power up, a hardware reset must be completed. ACD requires 132 MCLKs after reset to complete operation. The number of MCLKs is independent of the number of devices in the chain. Adjacent devices in the chain have their FS and FSD pins connected to each other. The master device's FS is connected to the FS pin of the DSP. The FSD pin on the last device in the chain is pulled high for master-slave configuration, and it is pulled low for stand-alone slave configuration. The master device has the highest address i.e., the master device has address equal to total no of channels in cascade minus 1. For example, if 8 devices are cascaded, then the master device has address 15 and 14 followed by the next device which has 13 and 12 etc. During the first 64 MCLKs, FS is configured as an output and FSD as an input. During the next 64 MCLKs, FS is configured as an input and FSD as an output. 24 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Functional Description (continued) The Master device always has its FS configured as an output and the last slave in the cascade (i.e. channel with address 0) always has its FSD configured as an input. To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between ACD starting (reset) and the FSD going high. During the next 64 MCLKs, the device counts the number of clocks till FS is pulled low. The sum total of the counts in the first phase and the second phase is the number of devices in the channel. For a cascaded system the rise time of H/W RESET must be less than the MCLK period and should satisfy setup time requirement of 2 ns with respect to MCLK rise-edge. If more than one codec is cascaded together, RESET must be synchronized to MCLK. Additionally all devices must see the same edge of MCLK within a window of 0.5 ns. This requirement does not exist for a single master or slave. MCLK and RESET can be asynchronous events. Power Management Most of the device (all except the digital interface) enters the power-down mode when D5 and D4, in control register 3A, are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, register contents are preserved and the output of the amplifier is held at midpoint voltage to minimize pops and clicks. The amount of power drawn during software power down is higher than during a hardware power down because of the current required to keep the digital interface active. Additional differences between software and hardware power-down modes are detailed in the following paragraphs. Software Power-Down Data bits D5 and D4 of control register 3A are used by TLV320AIC2x to turn on or off the software power-down mode, which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the software power-down, the digital interface circuit is still active while the internal ADC and DAC channel and all differential analog outputs are disabled, and DOUT is put in 3-state in the data frame only. Register data in the control frame is still accepted via DIN, but data in the data frame is ignored. The device returns to normal operation when D7 and D6 of control register 3A are reset. If the PLL is enabled (i.e., P is not set to 8), then executing a software power down and power up of the device causes the output drivers to go to the common-mode voltage. Therefore, before executing a software power down, the PLL must first be disabled (i.e., P should first be set to 8) before control register 3A is programmed. While bringing the codec out of software power down, the PLL should be re-enabled only after the codec is brought out of power down (i.e., register 3A must be programmed first followed by register 4). Hardware Power-Down The TLV320AIC2x requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, the device enters hardware power-down mode. In this state, the internal clock control circuit and the differential outputs are disabled. All other digital I/Os are disabled and DIN can not accept any data input. The device can only be returned to normal operation by holding PWRDN high. When not holding the device in the hardware power-down mode, PWRDN must be tied high. Smart Time Division Multiplexed Serial Port (SMARTDM) The SMART time division multiplexed serial port (SMARTDM) uses the four wires of DOUT, DIN, SCLK, and FS to transfer data into and out of the AIC2x. The TLV320AIC2xs SMARTDM supports three serial interface configurations (see Table 1): stand-alone master, stand-alone slave, and master-slave cascade, employing a time division multiplexed (TDM) scheme (a cascade of only-slaves is not supported). The SMARTDM allows for a serial connection of up to 8 stereo codecs to a single serial port. Data communication in the three serial interface configurations can be carried out in either standard operation (Default) or turbo operation. Each operation has two modes: programming mode (default mode) and continuous data transfer mode. To switch from the programming mode to the continuous data transfer mode, set bit D6 of control register 1 to 1, which is reset automatically after switching back to programming mode. The TLV320AIC2x can be switched back from the continuous data transfer mode to the programming mode by setting the LSB of the data on DIN to 1, only if the data format is (15+1), as selected by bit 0 of control register 1. The SMARTDM automatically adjusts the number 25 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Functional Description (continued) of time slots per frame sync (FS) to match the number of codecs in the serial interface so that no time slot is wasted. Both the programming mode and the continuous data transfer mode of the TLV320AIC2x are compatible with the TLV320AIC12. The TLV320AIC2x provides primary/secondary communication and continuous data transfer with improvements and eliminates the requirements for hardware and software requests for secondary communication as seen in the TLV320AIC10. The TLV320AIC2x continuous data transfer mode now supports both master/slave stand-alone and cascade. Table 1. Serial Interface Configurations TLV320AIC2x CONNECTIONS Stand-alone Master-slave cascade Slave-slave cascade M/S PIN MASTER High High NA SLAVE Low Low NA FSD PIN MASTER Pull high SLAVE Low Last slave's FSD pin is pulled high Not supported COMMENTS Connect to the next slave's FS (see Figure 23) NA NA Clock Source (MCLK, SCLK) MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout the device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in the master mode, SCLK and FS are output and derived from MCLK in order to provide clocking the serial communications between the device and a digital signal processor (DSP). When in the slave mode, SCLK and FS are inputs. SCLK is controlled by TURBO bit (D7) in control register 2. In the standard operation (non-turbo, TURBO = 0), SCLK frequency is defined by: * SCLK = (16 x FS x #Devices x mode) Where: * FS is the frame-sync frequency. #Device is the number of the codec channels in cascade. (#Device = 2 for stand-alone AIC2x) Mode is equal to 1 for continuous data transfer mode and 2 for programming mode. Serial Data Out (DOUT) DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data word is the ADC conversion result. In the control frame, the data is the register read results when requested by the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all zeroes. Valid data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The first bit transmitted on the falling edge of FS is the MSB of valid data. Serial Data In (DIN) The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of first SCLK after FS. In a data frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used, the LSB (D0) of every DAC channel is set to 1 to switch from the continuous data transfer mode to the programming mode. In a control frame, the data is the control and configuration data that sets the device for a particular function as described in Section 3.9, Control Register Programming. Frame-Sync FS The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pin is connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode). Data is valid on the falling edge of the FS signal. The frequency of FS is defined as the sampling rate of the TLV320AIC2x and derived from the master clock MCLK as followed (see Section 3.1 Operating Frequencies for details): * FS = MCLK / (16 x P x N x M) 26 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 0 SCLK (Output) 1 29 30 31 32 SCLKs FS DIN/DOUT (16 Bit) D15 MSB D14 D1 D0 LSB D15 MSB D14 D1 D0 LSB Master (CH 1) Slave (CH 2) Figure 19. Timing Diagram for FS in the Continuous Transfer Mode Cascade Mode and Frame-Sync Delayed (FSD) In cascade mode, the DSP should be in slave mode, i.e., it receives all frame-sync pulses from the master though the master's FS. The master's FSD is output to the first slave and the first slave's FSD is output to the second slave device and so on. Figure 20 shows the cascade of four TLV320AIC2xs in which the closest one to DSP is the master and the rest are slaves. The FSD output of each device is input to the FS terminal of the succeeding device. Figure 21 shows the FSD timing sequence in the cascade. 27 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com CLKOUT DR DX FSX FSR CLKX CLKR TMS320C5X TMS320C6X FS FS MCLK TLV320AIC20 DIN 1 DOUT SCLK FSD M/S 3.3 V MCLK To CLKOUT or External Oscillator TLV320AIC20 DIN 2 DOUT SCLK FSD M/S FS MCLK TLV320AIC20 DIN 3 DOUT SCLK FSD M/S FS MCLK TLV320AIC20 DIN 4 DOUT SCLK FSD IOVDD M/S Figure 20. Cascade Connection (to DSP Interface) Stand-Alone Slave In the stand-alone slave connection, the FS and SCLK inputs must be synchronized to each other and programmed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required to synchronize to the MCLK input but must remain active at all times to assure continuous sampling in the data converter. FSD must be connected to LOW for stand-alone-slave. FS is output for initial 132 MCLK and it is kept low. The host processor needs to keep the FS pin in high impedence state during this period to avoid contention. Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency) The AIC2x SMARTDM supports different sampling frequencies between the different channels in cascade, connecting to a single serial port in which all codecs are sampled at the same frequency of FS. For example: FS1 and FS2 are the desired sampling rates for CH1 and CH2 respectively: 1. FS = MCLK / (16 x M x N x P) 2. FS = n1 x FS1 (n1 = 1, 2, . . ., 8 defined in the control register 3A of CH1) 3. FS = n2 x FS2 (n2 = 1, 2, . . ., 8 defined in the control register 3A of CH2) 28 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 For validating the conversion data from this operation: * For DAC: The DSP needs to give the same data for n1 samples. CH1 picks one of the n1 samples. * For ADC: CH1 gives the same data for the n1 samples. DSP should pick one of the n1 samples. 0 SCLK (Output) 32 SCLKs FS 1 29 30 31 FSD DIN/DOUT (16 Bit) D15 MSB D14 D1 D0 LSB D15 MSB D14 D1 D0 LSB Master (CH 1) Slave (CH 2) Figure 21. Timing Diagram for FSD Output Master FS AIC20-1 AIC20-2 AIC20-3 AIC20-4 DIN/DOUT AIC20-1 FSD, AIC20-2 FS AIC20-2 FSD, AIC20-3 FS AIC20-3 FSD, AIC20-4 FS Slave0 Master Slave6 Slave5 Slave4 Slave3 Slave2 Slave1 Slave0 Master Slave6 Slave5 Slave4 16 Bits Figure 22. NOTE: AIC2x #4 FSD should be pulled high. Programming Mode In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains two frames as shown in Figures 3-10 and 3-11: data frame and control frame. The data frame contains data transmitted from the ADC or to the DAC. The control frame contains data to program each codec control register. The SMARTDM automatically sets the number of time slots per frame equal to the number of codec channels in the interface. Each time slot contains 16-bit data. The SCLK is used to perform data transfer for the serial interface between the AIC2x codecs and the DSP. The frequency of SCLK varies, depending on the selected mode of serial interface. In the stand alone-mode, there are 64 SCLKs (or four time slots) per sampling period. In the master-slave cascade mode, the number of SLCKs equals 32x(number of codec channels in the cascade). The digital output data from the ADC is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronization clock for the serial communication data and the frame-sync is taken from SCLK. The frame-sync signal that starts the ADC and DAC data transfer interval is taken from FS. The SMARTDM also provides a turbo operation, in which the FS's frequency is always the device's sampling frequency, but SCLK is running at a much higher speed. Thus, there are more than 64 SCLKs for each AIC2x per sampling period, in which the data frame and control frame occupy only the first 64 SCLKs from the falling edge of the frame-sync FS. 29 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com SCLK 64 SCLKS FS Data Frame DIN Slot 0 CH1 16-Bit DAC Slot 1 CH2 16-Bit DAC Control Frame Slot 2 CH1 Register Data Slot 3 CH2 Register Data DOUT CH1 16-Bit ADC CH2 16-Bit ADC CH1 Register Data CH2 Register Data Figure 23. Programming Mode: Stand-Alone Timing Slot Number SCLK 16 SCLKs Per Slot FS 0 1 2 2n-3 2n-2 2n-1 DIN/ DOUT Master Slave n-1 Slave n-2 Slave 3 Slave 2 Slave Master Slave 1 n-1 Slave n-2 Slave 3 Slave 2 Slave 1 Data Frame NOTE: n/2 is the total number of AIC20s in the cascade Control Frame (Register R/W) Figure 24. Standard Operation/Programming Mode: Master-Slave Cascade Timing Continuous Data Transfer Mode The continuous data transfer mode, selected by setting bit D6 of each codec's control register 1 to 1, contains conversion data only. In continuous data transfer mode, the control frame is eliminated, and the period of FS signal contains only the data frame in which the 16-bit data is transferred contiguously, with no inactivity between bits. The control frame can be reactivated by setting the LSB of DIN data to 1 if the data is in the 15+1 format. To return the programming mode in the 16-bit DAC data format mode, write 0 in bit D6 of each codec's control register 1 using I2C or S2C, or do a hardware reset to come out of continuous data transfer mode. If continuous data transfer mode needs to be used with turbo mode, then the codec should first be set in turbo mode before it is switched from the default programming mode to the continuous data transfer mode. SCLK 32 SCLKS FS Data Frame DIN Slot 0 CH1 16-Bit DAC Slot 1 CH2 16-Bit DAC Slot 0 CH1 16-Bit DAC Data Frame Slot 1 CH2 16-Bit DAC DOUT CH1 16-Bit ADC CH2 16-Bit ADC CH1 16-Bit ADC CH2 16-Bit ADC Figure 25. Standard Operation/Continuous Data Transfer Mode: Stand-Alone Timing 30 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Slot Number SCLK 0 1 2 n-3 n-2 n-1 0 1 2 n-3 n-2 n-1 16 SCLKs Per Time Slot FS DIN/ DOUT Master Slave n-1 Slave n-2 Slave 3 Slave 2 Slave Master Slave 1 n-1 Slave n-2 Slave 3 Slave 2 Slave 1 Data Frame / Sample 1 NOTE: n/2 is the total number of AIC20s in the cascade Data Frame / Sample 2 Figure 26. Standard Operation/Continuous Data Transfer Mode: Master-Slave Cascade Timing Turbo Operation (SCLK) Setting TURBO = 1 (bit D7) in each codec's control register 2 enables the AIC2x's turbo mode that requires the following condition to be met: * M x N > #Devices x mode Where: * M, N, and P are clock divider values defined in the control register 4. #Device is the number of codec channels in cascade. ( Number of Device = 2 for stand-alone AIC2x) Mode is equal to 1 for continuous data transfer mode and 2 for programming mode. The turbo operation is useful for applications that require more bandwidth for multitasking processing per sampling period. In the turbo mode (see Figure 27), the FS frequency is always the device's sampling frequency, but the SCLK is running at much higher speed. The output SCLK frequency is equal to (MCLK/P) and up to a maximum speed of 25 MHz. The data/control frame is still 32-SCLK long and the FS is one-SCLK pulse. If the AIC2x is in slave mode and the device is not set to turbo mode, only the first FS is used to synchronize the data transfer. The AIC2x ignores all subsequent FS signals and utilizes an internally generated FS. However, if the AIC2x is set to turbo mode while in slave mode, then the data transfer synchronizes on every FS signal. Therefore, it is recommended that if the AIC2x is set to slave mode, then the turbo mode is used. Also note that in turbo mode, it is recommended that SCLK should be a multiple of 32 x FS. 31 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com TURBO PROGRAMMING MODE Stand-Alone Case: Turbo SCLK ********************************************************************** Sampling Period FS Data Frame ADC/DAC Data Control Frame Register Data Hi-Z Master DIN / DOUT Master (CH 1) Slave (CH 2) Master (CH 1) Slave (CH 2) Cascade Case (Master + 4 Slaves): Turbo SCLK FS Data Frame DIN / DOUT ********************************************************** Sampling Period Control Frame Hi-Z Data Frame Control Frame TURBO CONTINUOUS DATA TRANSFER MODE Stand-Alone Case: Turbo SCLK ***************************************************** One SCLK FS Data Frame DIN / DOUT 15 14 Sampling Period Data Frame 0 ... 1 Hi-Z 15 14 ... 10 Hi-Z Cascade Case (Master + 4 Slaves): Turbo SCLK FS Data Frame DIN / DOUT Hi-Z ************************************************* Sampling Period Data Frame Hi-Z NOTE: SCLK is not drawn to scale. Figure 27. Timing Diagram for Turbo Operation 32 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Control Register Programming Each channel in the TLV320AIC2x contains six control registers that are used to program available modes of operation. All register programming occurs during the control frame through DIN. New configuration takes effect after a delay of one frame sync. The TLV320AIC2x is defaulted to the programming mode upon power up. Set bit 6 in control register 1 to switch to continuous data transfer mode. If the 15+1 data format of DIN has been selected, the LSB of the DIN to 1 to switch from continuous data transfer mode to programming set mode. Otherwise, either the device needs to be reset or the host port writes 0 to bit D6 of each codec's control register 1 during the continuous data transfer mode to switch back to the programming mode. The control registers are replicated for each channel in the AIC2x, and these need to be programmed separately for the individual channels. Register bits that control resources that are common to both channels are shadowed (i.e., writing to the appropriate register bit of one channel is automatically reflected in the register bits for the other channel). See the control register tables for a more detailed description of the exact register bits that are shadowed. Data Frame Format DIN (15+1) Bit Mode (Continuous Data Transfer Mode Only) D15 - D1 A/D and D/A Data DOUT (16 Bit A/D Data) D0 Control Frame Request D15 - D0 DIN 16 Bit Mode D15 - D0 A/D and D/A Data DOUT 16 Bit Mode D15 - D0 Figure 28. Data Frame Format Control Frame Format (Programming Mode) During the control frame, the DSP sends 16-bit words to each codec's time slot SMARTDM(TM) through DIN to read or write control registers in each codec shown in Table 4. The upper byte (Bits D15-D8) of the 16-bit control-frame word defines the read/write command. Bits D15-D13 define the control register address with register content occupied the lower byte D7-D0. Bit D12 is set to 0 for a write or to 1 for a read. Bit D11 in the write command is used to perform the broadcast mode. During a register write, the register content is located in the lower byte of DIN. During a register read, the register content is output in the lower byte of DOUT in the same control frame, whereas the lower byte of DIN is ignored. Broadcast Register Write Broadcast operation is very useful for a cascading system of SMARTDM codecs in which all register programming can be completed in one control frame. During the control frame and in any register-write time slot, if the broadcast bit (D11) is set to 1, the register content of that time slot is written into the specified register of all devices in cascade (see Figure 29). This reduces the DSP's overhead of doing multiple writes to program the same data into cascaded devices. 33 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Data to be Written Into Register DIN (Write) D15 D14 D13 0 D11 1 1 1 D7 - D0 Register R/W Broadcast Address DIN (Read) D15 D14 D13 1 X 1 1 1 Don't care D7 - D0 SMARTDM Device Address DOUT (Read) Register Address 0 Register Content D7 - D0 D15 D14 D13 D12 D11 D10 D9 Figure 29. Control Frame Data Format Master FS Data Frame AIC20 #1 AIC20 #2 Control Frame AIC20 #1 AIC20 #2 Data Frame DIN Slave0 Master Slave2 Slave1 Slave0 Master 001 0 1 111 Slave2 010 0 1 111 Slave1 100 0 1 111 Slave0 110 0 1 111 Master Slave2 Slave1 Slave0 Time Slot Write Command Reg Addr (D15-D13) R/W (D12) Broadcast (D11) D10-D8 A. NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1, Reg.2, Reg.4, and Reg.6 in all four DSP codecs of two TLV320AIC2xs in cascade (Master, Slave2, Slave1, and Slave0) during the same frame (i.e., register 1 of the four codecs contains the same data). Host Port Interface The host port uses a 2-wire serial interface (SCL, SDA) to program channel six of each of the codec control registers, and selectable protocol between S2C mode and I2C mode. The S2C is a write-only mode, and the I2C is a read-write mode selected by bits D1-D0 (HPC bits) of control register 2. If the host interface is not needed, the two pins of SCL and SDA can be programmed to become general-purpose I/Os. If selected to be used as I/O pins, the SDA and SCL pins become output and input pins respectively, determined by D1 and D0. Both S2C and I2C require a SMARTDM device address to communicate with the AIC2x. One of SMARTDM's advanced features is the automatic cascade detection (ACD) that enables SMARTDM to automatically detect the total number of codecs in the serial connection and use this information to assign each codec a distinct SMARTDM device address. Table 2 lists device addresses assigned to each codec in the cascade by the SMARTDM. The master always has the highest position in the cascade. For example in Figure 20, there is a total of 4 codecs in the cascade (i.e., one master and 3 slaves), then the device addresses in row 4 are used in which the master is codec 1 with a device address of 0000. 34 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Table 2. SMARTDM Device Addresses TOTAL CHANNELS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 CHANNELS POSITION IN CASCADE (1 CODEC HAS 2 CHANNELS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1110 1101 1101 1100 1100 1100 1011 1011 1011 1011 1010 1010 1010 1010 1010 1001 1001 1001 1001 1001 1001 1000 1000 1000 1000 1000 1000 1000 0111 0111 0111 0111 0111 0111 0111 0111 0110 0110 0110 0110 0110 0110 0110 0110 0110 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0100 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 0011 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 S C (Start-Stop Communication) The S2C is a write-only interface selected by programming bits D1-D0 of control register 2 to 01. The SDA input is normally in a high state, pulled low (START bit) to start the communication, and pulled high (STOP bit) after the transmission of the LSB. Figure 30 shows the timing diagram of S2C. The S2C also supports a broadcast mode in which the same register of all devices in cascade is programmed in a single write. To use S2C's broadcast mode, execute the following steps: 1. Write 111 1000 1111 1111 after the start bit to enable the broadcast mode. 2. Write data to program control register as specified in Figure 30 with bits D14-D11 = XXXX (don't care). 3. Write 111 1000 0000 0000 after the start bit to disable the broadcast mode. SCL SDA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SMARTDM Device Start Bit = 0 Address (see Table 3-1) Register Address Register Content Stop Bit = 1 Figure 30. S2C Programming 35 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com I2C * Each I2C read-from or write-to each codec control register is given by an index register address. * Read/write sequence always starts with the first byte as I2C address followed by 0. During the second byte, default/broadcast mode is set and the index register address is initialized. For write operation control register, data to be written is given from the third byte onwards. For read operation, stop-start is performed after the second byte. Now the first byte is I2C address followed by 1. From the second byte onwards, control register data appears. * Each time read/write is performed, the index register address is incrimented so that the next read/write is performed on the next control register. * During the first write cycle and all write cycles in the broadcast, only the device with address 0000 issues ACK to the I2C. * Similarly, for a register with multiple sub-registers the sub-register index automatically increments with each read/write. For example, the first read/write to register 3 read/writes to register 3A, the next to register 3B and so forth until the last sub-register is reached. At this time the sub-register index wraps back around to the first sub-register I2C Write Sequence SCL SDA A6 A5 A4 A3 A2 A1 A0 0 ACK B7 B6 B5 B4 B3 R2 R1 R0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Bit = 0 SMARTDM Device Index Register Address 00000 = Default Address (Index) Control Register Data for Write 11111 = Broadcast Mode (see Table 3-1) (Index) Programmable 12C Device Address Set by Control Register 2 I2C I2C I2C 654 Control Register Data for Write (Index+1) Figure 31. I2C Write Sequence I C Read Sequence SCL 2 SDA Start Bit = 0 A6 A5 A4 A3 A2 A1 A0 0 ACK B7 B6 B5 B4 B3 R2 R1 R0 ACK I2C 6 I2C 5 I2C 4 xxxxx = Don't Care Index Register Address (Index) Stop Bit = 1 SMARTDM Device Address (see Table 1) 2 Programmable 1 C Device Address Set by Control Register 2 SCL SDA A6 A5 A4 A3 A2 A1 A0 1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Bit = 0 I2C 6 I2C 5 2 I2C 4 SMARTDM Device Address (see Table 1) Programmable 1 C Device Address Set by Control Register 2 Control Register Data (Index) Control Register Data (Index+1) Figure 32. I2C Read Sequence Each codec has an index register address. To perform a write operation, make the LSB of the first byte as 0 (write) (see Figure 33). During the second byte, the index register address is initialized and mode (broadcast/default) is set. From the third byte onwards, write data to the control register (given by index register) and increment the index register until stop or repeated start occurs. For operation, make the LSB of the first byte as 1 (read). From the second byte onwards, AIC starts transmitting data from the control register (given by the index register) and increments the index register. For setting the index register perform operation the same as write case for 2 bytes, and then give a stop or repeated start. 36 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 * S/Sr -> Start/Repeated Start. Write Mode 7 Bit S/Sr I2C Device Address (3 Bit)+ 1 Bit R/W Ack SMARTDM Device Address + = 0 Default/Broadcast (00000/11111) 8 Bit Mode (5 Bit) + Index Register Address (3 Bit) Ack 8 Bit Control Register Data (Write) Ack Increment Index Register Address 8 Bit Control Register Data (Write) Read Mode 7 Bit S/Sr I2C Device Address (3 Bit)+ 1 Bit R/W Ack SMARTDM Device Address + = 1 8 Bit To the Address Given To the Address Given by Index Register by Index Register Address Address Increment Index Increment Index Register Address Register Address 8 Bit Ack Control Register Data (Read) Ack Control Register Data (Read) From the Address Given by Index Register Address From the Address Given by Index Register Address Stop For Initializing Index Register Address 7 Bit S/Sr I2C Device Address (3 Bit)+ SMARTDM Device Address + 1 Bit R/W Ack =0 8 Bit Mode (5 Bit) + Index Register Address (3 Bit) Ack Figure 33. Index Register Addresses Register Map Each AIC2x codec consists of 2 channels. Each channel has 6 registers to enable the user to control various components. Registers that control resources that are common across the two channels are shadowed. This means that writing to the appropriate register in one channel automatically updates the contents of the same register in the other channel to reflect the change. For example, writing to register 4 in channel 1 automatically updates the contents of register 4 for channel 2 and vice versa. Refer to the individual register description for a more detailed description of the exact register bits that are shadowed. Bits D15 through D13 represent the control register address that is written with data carried in D7 through D0. Bit D12 determines a read or a write cycle to the addressed register. When D12 = 0, a write cycle is selected. When D12 = 1, a read cycle is selected. Bit D11 controls the broadcast mode as described above, in which the broadcast mode is enabled if D11 is set to 1. Always write 1s to the bits D10 through D8. Table 3 shows the register map. Table 3. Register Map D15 D14 D13 D12 RW D11 BC D10 1 D9 1 D8 1 D7 D6 D5 D4 D3 D2 D1 D0 Register Address Control Register Content Table 4. Register Addressing REGISTER NO. 0 1 2 3 4 5 6 D15 0 0 0 0 1 1 1 D14 0 0 1 1 0 0 1 D13 0 1 0 1 0 1 0 REGISTER NAME No operation Control 1 Control 2 Control 3 Control 4 Control 5 Control 6 37 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Control Register Content Description Control Register 1 (1) D7 ADOVF R (1) D6 CX R/W/S D5 IIR R/W D4 DAOVF R D3 BIASV R/W/S D2 ALB R/W D1 DLB R/W D0 DAC16 R/W/S NOTE: R = Read, W = Write, S = Shadowed Control Register 1 Bit Summary BIT D7 NAME ADOVF RESET VALUE 0 FUNCTION ADC over flow. This bit indicates whether the ADC is overflow. ADOVF = 0 No overflow ADOVF = 1 A/D is overflow. Continuous data transfer mode. This bit selects between programming mode and continuous data transfer mode. CX = 0 Programming mode CX = 1 Continuous data transfer mode IIR Filter. This bit selects between FIR and IIR for decimation/interpolation low-pass filter. IIR = 0 FIR filter is selected IIR = 1 IIR filter is selected. DAC over flow. This bit indicates whether the DAC is overflow DAOVF = 0 No overflow DAOVF = 1 DAC is overflow Bias voltage. This bit selects the output voltage for BIAS pin BIASV = 0 BIAS pin = 1.35 V BIASV = 1 BIAS pin = 2.35 V Analog loop back ALB = 0 Analog loopback disabled ALB = 1 Analog loopback enabled Digital loop back DLB = 0 Digital loopback disabled DLB = 1 Digital loopback enabled DAC 16-bit data format. This bit applies to the continuous data transfer mode only to enable the 16-bit data format for DAC input.DAC16 = 0 DAC input data length is 15 bits. Writing a 1 to the LSB of the DAC input to switch from continuous data transfer mode to programming mode. DAC16 = 1 DAC input data length is 16 bit. D6 CX 0 D5 IIR 0 D4 DAOVF 0 D3 BIASV 0 D2 ALB 0 D1 DLB 0 D0 DAC16 0 Control Register 2 (1) D7 TURBO R/W/S (1) D6 DIFBP R/W/S D5 I2C6 R/W/S D4 I2C5 R/W/S D3 I2C4 R/W/S D2 GPO R/W/S R/W/S D1 HPC R/W/S D0 NOTE: R = Read, W = Write, S = Shadowed Control Register 2 Bit Summary BIT D7 NAME TURBO RESET VALUE 0 FUNCTION Turbo mode. This bit is used to set the SCLK rate. TURBO = 0 SCLK = (16 x FS x number of device x mode) TURBO = 1 SCLK = MCLK/P (P is determined in register 4) Decimation/interpolation filter bypass. This bit is used to bypass both decimation and interpolation filters. DIFBP = 0 Decimation/interpolation filters are operated. DIFBP = 1 Decimation/interpolation filters are bypassed. I2C device address. These three bits are programmable to define three MSBs of the I2C device address (reset value is 100). These three bits are combined with the 4-bit SMARTDM device address to form 7-bit I2C device address. D6 DIFBP 0 D5-D3 I2Cx 100 38 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Control Register 2 Bit Summary (continued) BIT D2 D1-D0 NAME GPO HPC RESET VALUE 0 00 General-purpose output Host port control bits. Write the following values into D1-D0 to select the appropriate configuration for two pins SDA and SCL. The SDA and SCL pins are used for I2C interface if D1-D0 = 00. The SDA and SCL pins are used for S2C interface if D1-D0 = 01. If D1-D0 = 10, the SDA pin = D2, input going into the SCL pin is output to DOUT (11), the SDA pin = control frame flag. FUNCTION Control Register 3A (1) D7 00 R/W (1) NOTE: R = Read, W = Write D6 D5 PWDN R/W D4 D3 SWRS R/W/S D2 D1 ASRF R/W D0 Control Register 3A Bit Summary BIT NAME RESET VALUE Power down PWDN = 00 No power down PWDN = 01 Power-down A/DPWDN = 10 Power-down D/APWDN = 11 Software power down the entire device Software reset. Set this bit to 1 to reset the device. Asynchronous sampling rate factor. These three bits define the ratio n between FS frequency and the desired sampling frequency fs (Applied only if different sampling rate between CODEC1 and CODEC2 is desired) ASRF = 001, n = FS/fs = 1 ASRF = 010, n = FS/fs = 2 ASRF = 011, n = FS/fs = 3 ASRF = 100, n = FS/fs = 4 ASRF = 101, n = FS/fs = 5 ASRF = 110, n = FS/fs = 6 ASRF = 111, n = FS/fs = 7 ASRF = 000, n = FS/fs = 8 FUNCTION D5-D4 PWDN 00 D3 SWRS 0 D2-D0 ASRF 001 Control Register 3B (1) D7 01 R/W (1) NOTE: R = Read, W = Write D6 D5 8KBF R/W D4 Reserved D3 MHNS D2 MHDS R/W/S D1 MLDO D0 MSPK Control Register 3B Bit Summary BIT D5 D4 D3 NAME 8KBF Reserved MHNS RESET VALUE 0 0 0 Mute handset. This bit controls the MUTE function of handset output driver. MHNS = 0 Handset output driver is not MUTE. MHNS = 1 Handset output driver is MUTE. Mute headset. This bit controls the MUTE function of headset output driver. MHDS = 0 Headset output driver is not MUTE. MHDS = 1 Headset output driver is MUTE. Mute line output. This bit controls the MUTE function of the 600- output driver. MLNO = 0 The 600- output driver is not MUTE. MLNO = 1 The 600- output driver is MUTE. Mute 8- speaker. This bit controls the MUTE function of the 8- speaker driver. MSPK = 0 The 8- speaker driver is not MUTE. MSPK = 1 The 8- speaker driver is MUTE. 39 FUNCTION 8 kHz band pass filter. Set this bit to 1 to enable the band-bass filter [300 Hz -3.3 kHz] with the sampling rate at 8 kHz. D2 MHDS 0 D1 MLNO 0 D0 MSPK 0 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Control Register 3C (1) D7 10 R/W (1) NOTE: R = Read, W = Write, S = Shadowed D6 D5 Reserved D4 D3 ICID R/W/S D2 D1 OSR R/W D0 Control Register 3C Bit Summary BIT D5 NAME Reserved RESET VALUE 0 Chip ID. These two bits represent the device version number. ICID = 000 Version 1 ICID = 001 Version 2 ICID = 010 Version 3 ICID = 011 Version 4 ICID = 100 Version 5 ICID = 101 Version 6 ICID = 110 Version 7 ICID = 111 Version 8 OSR option D1-D0 = X1 OSR for DAC Channel is 512 (Max FS = 8 Ksps) D1-D0 = 10 OSR for DAC Channel is 256 (Max FS = 16 Ksps) D1-D0 = 00 OSR for DAC Channel is 128 (Max FS = 26 Ksps) FUNCTION D4-D2 ICID 000 D1-D0 OSR option 00 Control Register 3D (1) D7 11 R/W (1) NOTE: R = Read, W = Write, S = Shadowed D6 D5 D4 D3 LCDAC R/W/S D2 D1 D0 Control Register 3D Bit Summary BIT D5-D0 (1) NAME LCDAC (1) RESET VALUE FUNCTION 000000 LCD DAC. These bits represent the input value for the 6-bit LCD DAC. NOTE: See the Electrical Characteristics table for LCD DAC specification. Control Register 4 (1) D7 FSDIV R/W (1) R/W/S R/W/S R/W/S D6 D5 D4 D3 MNP R/W/S R/W/S R/W/S R/W/S D2 D1 D0 NOTE: R = Read, W = Write, S = Shadowed Control Register 4 Bit Summary BIT D7 NAME FSDIV RESET VALUE 0 FUNCTION Frame sync division factor FSDIV = 0 To write value of P to bits D2-D0 and value of N to bits D6-D3 FSDIV = 1 To write value of M to bits D6-D0 40 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Control Register 4 Bit Summary (continued) BIT NAME RESET VALUE FUNCTION Divider values of M, N, and P to be used in junction with the FSDIV bit for calculation of FS frequency according to the formula: FS = MCLK / (16 x M x N x P) where: M = 1, 2, .., 128 Determined by D6-D0 with FSDIV = 1 D7-D0 = 10000000 M = 128 D7-D0 = 10000001 M = 1 D7-D0 = 11111111 M = 127 N = 1, 2,.., 16 Determined by D6-D3 with FSDIV = 0, D6-D0 M, N, P D7-D0 = 00000xxx N = 16 D7-D0 = 00001xxx N = 1 D7-D0 = 01111xxx N = 15 P = 1, 2,.., 8 Determined by D2-D0 with FSDIV = 0 D7-D0 = 0xxxx000 P = 8 D7-D0 = 0xxxx001 P = 1 D7-D0 = 0xxxx111 P = 7 D6-D0 MNP -- Control Register 5A (1) D7 0 R/W (1) D6 0 R/W R/W R/W R/W D5 D4 D3 ADPGA R/W R/W R/W D2 D1 D0 NOTE: R = Read, W = Write Table 5. A/D PGA Gain D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADPGA ADC input PGA gain = MUTE ADC input PGA gain = 54 dB ADC input PGA gain = 48 dB ADC input PGA gain = 42 dB ADC input PGA gain = 40.5 dB ADC input PGA gain = 39 dB ADC input PGA gain = 37.5 dB ADC input PGA gain = 36 dB ADC input PGA gain = 34.5 dB ADC input PGA gain = 33 dB ADC input PGA gain = 31.5 dB ADC input PGA gain = 30 dB ADC input PGA gain = 28.5 dB ADC input PGA gain = 27 dB ADC input PGA gain = 25.5 dB ADC input PGA gain = 24 dB ADC input PGA gain = 22.5 dB ADC input PGA gain = 21 dB ADC input PGA gain = 19.5 dB ADC input PGA gain = 18 dB ADC input PGA gain = 16.5 dB ADC input PGA gain = 15 dB ADC input PGA gain = 13.5 dB ADC input PGA gain = 12 dB ADC input PGA gain = 10.5 dB ADC input PGA gain = 9 dB ADC input PGA gain = 7.5 dB 41 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Table 5. A/D PGA Gain (continued) D5 0 0 0 0 0 D4 0 0 0 0 0 D3 0 0 0 0 0 D2 1 0 0 0 0 D1 0 1 1 0 0 D0 0 1 0 1 0 ADC input PGA gain = 6 dB ADC input PGA gain = 4.5 dB ADC input PGA gain = 3 dB ADC input PGA gain = 1.5 dB ADC input PGA gain = 0 dB ADPGA Control Register 5B (1) D7 0 R/W (1) D6 1 R/W R/W R/W R/W D5 D4 D3 DAPGA R/W R/W R/W D2 D1 D0 NOTE: R = Read, W = Write D/A PGA Gain D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DAPGA DAC input PGA gain = MUTE DAC input PGA gain = -54 dB DAC input PGA gain = -48 dB DAC input PGA gain = -42 dB DAC input PGA gain = -40.5 dB DAC input PGA gain = -39 dB DAC input PGA gain = -37.5 dB DAC input PGA gain = -36 dB DAC input PGA gain = -34.5 dB DAC input PGA gain = -33 dB DAC input PGA gain = -31.5 dB DAC input PGA gain = -30 dB DAC input PGA gain = -28.5 dB DAC input PGA gain = -27 dB DAC input PGA gain = -25.5 dB DAC input PGA gain = -24 dB DAC input PGA gain = -22.5 dB DAC input PGA gain = -21 dB DAC input PGA gain = -19.5 dB DAC input PGA gain = -18 dB DAC input PGA gain = -16.5 dB DAC input PGA gain = -15 dB DAC input PGA gain = -13.5 dB DAC input PGA gain = -12 dB DAC input PGA gain = -10.5 dB DAC input PGA gain = -9 dB DAC input PGA gain = -7.5 dB DAC input PGA gain = -6 dB DAC input PGA gain = -4.5 dB DAC input PGA gain = -3 dB DAC input PGA gain = -1.5 dB DAC input PGA gain = 0 dB 42 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Control Register 5C (1) D7 1 D6 0 R/W (1) NOTE: R = Read, W = Write R/W D5 D4 ASTG R/W R/W R/W D3 D2 D1 DSTG R/W R/W D0 Analog Sidetone Gain D5 1 1 1 1 0 0 0 0 D4 1 1 0 0 1 1 0 0 D3 1 0 1 0 1 0 1 0 Analog sidetone gain = MUTE Analog sidetone gain = -27 dB Analog sidetone gain = -24 dB Analog sidetone gain = -21 dB Analog sidetone gain = -18 dB Analog sidetone gain = -15 dB Analog sidetone gain = -12 dB Analog sidetone gain = -9 dB DSTG Digital Sidetone Gain D2 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 Digital sidetone gain = MUTE Digital sidetone gain = -27 dB Digital sidetone gain = -24 dB Digital sidetone gain = -21 dB Digital sidetone gain = -18 dB Digital sidetone gain = -15 dB Digital sidetone gain = -12 dB Digital sidetone gain = -9 dB DSTG Control Register 5D (1) D7 1 R/W (1) D6 1 R/W D5 SPKG R/W/S D4 D3 D2 Reserved R/W D1 D0 NOTE: R = Read, W = Write Control Register 5D Bit Summary BIT NAME RESET VALUE Speaker Gain SPKG = 00 0 dB Gain SPKG = 01 1 dB Gain SPKG = 10 2 dB Gain SPKG = 11 3 dB Gain FUNCTION D5-D4 SPKG 00 D3-D0 Reserved 0000 Control Register 6A (1) D7 0 R/W (1) D6 HDSI2O R/W/S D5 HNSI2O R/W/S D4 CIDI R/W D3 LINEI R/W D2 MICI R/W D1 HNSI R/W D0 HDSI R/W NOTE: R = Read, W = Write 43 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Control Register 6A Bit Summary BIT D6 NAME HDSI2O RESET VALUE 0 FUNCTION Headset input to output HDSI2O = 0 The headset input is not connected to the headset output. HDSI2O = 1 The headset input is connected to the headset output. Handset input to output HNSI2O = 0 The handset input is not connected to the handset output. HNSI2O = 1 The handset input is connected to the handset output. Caller ID input select CIDI = 0 The caller ID input is not connected to ADC channel. CIDI = 1 The caller ID input is connected to ADC channel. Line input select LINEI = 0 The line driver input is not connected to ADC channel. LINEI = 1 The line driver input is connected to ADC channel. MIC input select MICI = 0 The microphone input is not connected to ADC channel. MICI = 1 The microphone input is connected to ADC channel. Handset input select HNSI = 0 The handset input is not connected to ADC channel. HNSI = 1 The handset input is connected to ADC channel Headset input select HDSI = 0 The headset input is not connected to ADC channel. HDSI = 1 The headset input is connected to ADC channel. D5 HNSI2O 0 D4 CIDI 0 D3 LINEI 0 D2 MICI 0 D1 HNSI 0 D0 HDSI 0 Control Register 6B (1) D7 1 R/W (1) D6 Reserved R D5 ASTOHD R/W D4 ASTOHN R/W D3 SPKO R/W D2 LINEO R/W D1 HNSO R/W D0 HDSO R/W NOTE: R = Read, W = Write Control Register 6B Bit Summary BIT D6 D5 NAME Reserved ASTOHD RESET VALUE 0 0 Analog sidetone output select for headset. This bit connects the analog sidetone to headset output. ASTOHD = 0. The analog sidetone is not connected to headset output. ASTOHD = 1. The analog sidetone is connected to headset output. Analog sidetone output select for handset. This bit connects the analog sidetone to handset output. ASTOHN = 0. The analog sidetone is not connected to handset output. ASTOHN = 1. The analog sidetone is connected to handset output. Speaker output select. This bit connects the DAC output to the 8- speaker driver SPKO = 0 The speaker driver output is not connected to DAC channel. SPKO = 1 The speaker driver output is connected to DAC channel. Line output select. This bit connects the DAC output to the 600- line driver LINEO = 0 The line driver output is not connected to DAC channel. LINEO = 1 The line driver output is connected to DAC channel. Handset output select. This bit connects the DAC output to the 150- handset driver HNSO = 0 The handset driver output is not connected to DAC channel. HNSO = 1 The handset driver output is connected to DAC channel. Headset output select. This bit connects the DAC output to the 150- headset driver HDSO = 0 The headset driver output is not connected to DAC channel. HDSO = 1 The headset driver output is connected to DAC channel. FUNCTION D4 ASTOHN 0 D3 SPKO 0 D2 LINEO 0 D1 HNSO 0 D0 HDSO 0 44 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Layout and Grounding Guidelines for TLV320AIC2x TLV320AIC2x has a built-in analog antialias filter, which provides rejection to external noise at high frequencies that may couple into the device. Digital filters with high out-of-band attenuation also reject the external noise. If the differential inputs are used for the ADC channel, then the noise in the common-mode signal is also rejected by the high CMRR of TLV320AIC2x. Using external common-mode for microphone inputs also helps reject the external noise. However to extract the best performance from TLV320AIC2x, care must be taken in board design and layout to avoid coupling of external noise into the device. TLV320AIC2x supports clock frequencies as high as 100 MHz. To avoid coupling of fast switching digital signals to analog signals, the digital and analog sections should be separated on the board. In TLV320AIC2x the digital and analog pins are kept separated to aid such a board layout. A separate analog ground plane must be used for the analog section of the board. The analog and digital ground planes should be shorted at only one place as close to TLV320AIC2x as possible. No digital trace should run under TLV320AIC2x to avoid coupling of external digital noise into the device. It is suggested to have the analog ground plane running below the TLV320AIC2x. The power-supplies must be decoupled close to the supply pins, preferably, with 0.1 F ceramic capacitor and 10 F tantalum capacitor following. The ground pin must be connected to the ground plane as close as possible to the TLV320AIC2x, so as to minimize any inductance in the path. Since the MCLK is expected to be a very high frequency signal, it is advisable to shield it with digital ground. For best performance of ADC in differential input mode, the differential signals must be routed close to each other in similar fashion, so that the noise coupling on both the signals is the same and can be rejected by the device. Extra care has to be taken for the speaker driver outputs, as any trace resistance can cause a reduction in the maximum swing that can be seen at the speaker. TLV320AIC2x-to-DSP Interface The TLV320AIC2x interfaces gluelessly to the McBSP port of a C54x or C6x TI DSP. Figure 34 shows a single TLV320AIC2x connected to a C54x or C6x TI DSP. DX DR FSX FSR FS MCLK DIN TLV320AIC20 DOUT SCLK CLKR TMS320C54X TMS320C6X M/S IOVDD From Oscillator CLKX Figure 34. TLV320AIC2xs Interface to McBSP Port of C54x or C6x DSP Hybrid Circuit External Connections The TLV320AIC2x connected to the telephone line using the LINEI and LINEO hybrid circuit is shown in Figure 35. 45 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Layout and Grounding Guidelines for TLV320AIC2x (continued) 68 kW LINEI+ LINEI- 10 kW 68 kW 10 kW Line 136 kW 136 kW 300 W LINEO+ 600 W LINEO- 300 W Figure 35. Hybrid Circuit External Connections Microphone, Handset, and Headset External Connections The microphone, headset, and handset external connections are shown in Figure 36. The suggested discrete components with their values also are included. MICBIAS 2 mA max, 2.35 V 0.1 F MICI+ (1.35 V) 0.1 F MICIMIC AVSS HEADSET/HANDSET Preamp 0.1 F HDSI+ HNSI+ (1.35 V) HDSIHNSI10 k MIC Preamp 10 k 10 k 10 k 10 k 0.1 F 10 k MIC AVSS TLV320AIC20 Figure 36. MIC/Handset/Headset External Connections 46 www.ti.com TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 Layout and Grounding Guidelines for TLV320AIC2x (continued) CallerID Interface The callerID amplifier interface to the telephone line is shown in (A). The value for Rx is 365 k (E96 series, which has 1% tolerance). Cx is 470 pF (10% tolerance) of high-voltage rating. Voltage rating is decided based on the telecommunication standards of the country. The typical value is 1 kV. The callerID input can be used as a lower-performance line input. For this application, a larger value capacitor is required for Cx. To Telephone VCOM 0-dB Gain, Typ. To Analog Crosspoint TLV320AIC20 VCOM A. Typical Application Circuit for CallerID Amplifiers To RJ11 Cx Rx 470 pF CIDI+ 365 k CIDI- Rx Cx 365 k 470 pF Figure 37. Recommended Power-Supply Decoupling The recommended power-supply decoupling for the TLV320AIC2x is shown in Figure 38. Both high frequency and bulk decoupling capacitors are suggested. The high-frequency capacitors should be X7R type capacitors or better. A 1-F ceramic capacitor should be used to decouple the digital power supply. 47 TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363C - MARCH 2002 - REVISED MARCH 2005 www.ti.com Layout and Grounding Guidelines for TLV320AIC2x (continued) IOVDD 12 0.1 F TLV320AIC20 IOVDD 0.01 F 13 IOVSS 1 F DGND DVDD 15 0.1 F AVDD2 0.1 F 0.01 F 16 5 0.1 F AGND 27 0.1 F AGND AVDD 33 0.1 F AVDD AGND 42 0.1 F AGND 43 AVDD AVSS 32 AVDD1 AVSS1 25 29 DRVDD DRVSS1 DRVSS2 6 DVDD DVSS DGND AVDD2 AVSS2 DRVDD DVDD = Digital Power DGND = Digital Ground AVDD/AVDD1/AVDD2= Analog Power AGND = Analog Ground DRVDD = Separate Analog Power Figure 38. Recommended Decoupling 48 PACKAGE OPTION ADDENDUM www.ti.com 18-Mar-2005 PACKAGING INFORMATION Orderable Device TLV320AIC20CPFB TLV320AIC20CPFBR TLV320AIC20IPFB TLV320AIC20IPFBR TLV320AIC21CPFB TLV320AIC21CPFBR TLV320AIC21CPFBRG4 TLV320AIC21IPFB TLV320AIC21IPFBR TLV320AIC24CPFB TLV320AIC24CPFBR TLV320AIC24IPFB TLV320AIC24IPFBR TLV320AIC25CPFB TLV320AIC25CPFBR TLV320AIC25IPFB TLV320AIC25IPFBR (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Package Drawing PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB PFB Pins Package Eco Plan (2) Qty 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 250 1000 250 1000 250 1000 TBD TBD TBD TBD TBD TBD Lead/Ball Finish Call TI Call TI Call TI Call TI Call TI Call TI CU NIPDAU Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI MSL Peak Temp (3) Call TI Call TI Call TI Call TI Call TI Call TI Level-2-260C-1 YEAR Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI 1000 Green (RoHS & no Sb/Br) 250 1000 250 1000 250 1000 250 1000 250 1000 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A - JANUARY 1995 - REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,50 36 25 0,27 0,17 0,08 M 37 24 48 13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0- 7 12 1,20 MAX 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 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